1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device and a method of producing the same, more particularly relates to a semiconductor nonvolatile memory device having nonvolatile memory cell of floating gate type MOS transistors and a method of producing the same.
2. Description of the Related Art
In recent years, as semiconductor nonvolatile memory devices, there have been active development and commercialization of erasable programmable read-only memories (EPROM) using floating gate type MOS transistors, electrically erasable programmable read-only memories (EEPROM), flash memories, ones of EEPROMS, adopting full erasure methods, etc.
The above-mentioned flash memories include NOR type flash memories and NAND type flash memories. The former use single floating gate type MOS transistor as the memory cell of the flash memory, while the latter use a NAND cell comprised of adjoining memory cells comprised of a plurality of, for example, N number of floating gate type MOS transistors as a unit cell.
Such NAND type flash memories are slower in speed of random access compared with NOR type flash memories, but are superior in terms of degree of integration, so have been developed and commercialized in recent years as flash memories for increasing the degree of integration.
A sectional view of an example of the above floating gate type of semiconductor nonvolatile memory device is shown in FIG. 1. A gate insulating film (tunnel insulating film) 20a comprised of for example a thin film of silicon oxide is formed on an active region of a semiconductor substrate 10 isolated by an element isolation insulating film 24a formed by for example the LOCOS method. A floating gate 30b comprised of for example polycrystalline silicon is formed at an upper layer. Further, an inter-layer insulating film 25a comprised of for example an oxide-nitride-oxide stacked insulating film (ONO film) is formed at an upper layer thereof. At an upper layer of the inter-layer insulating film 25a is formed a control gate 31 of a polycide structure comprised of for example a lower control gate 31a of polycrystalline silicon and an upper control gate 31b of tungsten silicide. In the semiconductor substrate 10, not shown source-drain diffusion layers are formed at the two sides of the control gate 31. Due to this, a field effect transistor is comprised, having a floating gate 30b covered by an insulating film between the control gate 31 and the channel formation region In the semiconductor substrate 10.
In the floating gate type semiconductor nonvolatile memory device having the above structure, the floating gate 30b has the function of holding the charge in the film while the gate insulating film 20a and the inter-layer insulating film 25a have the role of sealing the charge in the floating gate 30b. When a suitable voltage is applied to the control gate 31, semiconductor substrate 10, source-drain diffusion layer, etc., a Fowler-Nordheim type tunnel current (FN current) is caused, a charge is injected through a gate insulating film 20a from the semiconductor substrate 10 to the floating gate 30b, or a charge is released from the floating gate 30b to the semiconductor substrate 10.
If a charge is stored in the floating gate 30b, a field is generated by the stored charge, therefore threshold voltage of the transistor changes. Data can be stored by this change. For example, it is possible to erase data by storing a charge in the floating gate 30b or to write data by releasing the charge stored in the floating gate 30b. 
The floating gate type semiconductor nonvolatile memory device of the above related art, however, has an overlap portion I as a margin for connection of the floating gate 30b and the element isolation insulating film 24a. In particular, an element isolation insulating film obtained by the LOCOS method has a bird""s beak, so the element isolation width becomes greater and the isolation voltage resistance falls. This makes it difficult to reduce the cell area.
To solve the above problem, a floating gate type semiconductor nonvolatile memory device having a self-aligned shallow trench isolation (SA-STI) cell structure which forms an element isolation region by self-alignment at the end of the floating gate in the width direction has been developed (see IEDM Tech. Dig. 1994, pp. 61 to 64). Below, an explanation will be made of a NAND type semiconductor nonvolatile memory device having an SA-STI cell structure. FIG. 2A is a plan view of this. A floating gate FG covered by an insulating film is formed between a control gate CG and channel formation region of the silicon semiconductor substrate at a region where an active region of the silicon semiconductor substrate isolated by a trench type element isolation insulating film TI intersects the control gate CG to form a word line. Further, source-drain diffusion regions SD are formed in the substrate at the two sides of the control gate CG. A plurality of field effect transistors having floating gates FG covered by an insulating film between the control gate CG and the channel formation region in the semiconductor substrate, that is, memory transistors MT, are connected in series to form a NAND column. A selection MOS transistor ST for selecting the NAND column is formed at the other end of the NAND column and has a drain diffusion layer connected through a bit contact BC to a not shown bit line. A not shown selection MOS transistor is also formed at the other end of the NAND column and has a source diffusion layer connected to the source line S.
An equivalent circuit diagram of the semiconductor nonvolatile memory device shown in the plan view of FIG. 18A is shown in FIG. 2B. Memory transistors (MT1a, MT2a, MT3a, . . . ) are connected in series to form a NAND column. A selection MOS transistor STa for selecting the NAND column is formed at one end of the NAND column and has a drain diffusion layer connected through the bit contact BCa to the bit line BLa. A not shown selection MOS transistor is formed at the other end of the NAND column and has a source diffusion layer connected through a sub source line Sa to a main source line S. Another NAND column comprised of a memory transistor MT1axe2x80x2 etc. selectable by a selection MOS transistor STaxe2x80x2 is also connected to the bit line BLa. On the other hand, memory transistors (MT1b, MT2b, MT3b, . . . ) are connected in series to form a NAND column. A selection MOS transistor STb for selection of this NAND column is formed at one end of this NAND column and has a drain diffusion layer connected through the bit contact BCb to the bit line BLb. The source diffusion layer of a not shown selection MOS transistor formed at the other end of the NAND column is connected through a sub source line Sb to the main source line S.
A sectional view along the line A-Axe2x80x2 in FIG. 2A of the semiconductor nonvolatile memory device is shown in FIG. 3A and a sectional view along the line B-Bxe2x80x2 is shown in FIG. 3B. As shown in FIG. 3A, a gate insulating film (tunnel insulating film) 20a comprised of, for example, a thin film of silicon oxide is formed on an active region of the semiconductor substrate 10 isolated by a trench type element isolation insulating film 24a. A floating gate 30b comprised of for example polycrystalline silicon is formed at the upper layer. Further, an inter-layer insulating film 25a comprised of for example an ONO film is formed at an upper layer of this. A control gate (word line) 31 covering the upper surface of the inter-layer insulating film 25a and comprised of for example polycrystalline silicon is formed. Further, as shown in FIG. 3B, source-drain diffusion layers 13 are formed in the semiconductor substrate 10 at the two sides of a control gate 31. Due to this, a field effect transistor having a floating gate 30b covered by an insulating film between the control gate 31 and the channel formation region in the semiconductor substrate 10 is formed. The transistors are connected in series in a NAND format to form a NAND column.
A selection transistor formed with a control gate of the memory cell as a gate electrode for example is connected to one end of the NAND column. The selection transistor and the memory transistors constituting the NAND column are for example covered by an inter-layer insulating film 28 comprised of for example silicon oxide. The inter-layer insulating film 28 has a bit contact hole BC formed in it reaching the drain diffusion region 13xe2x80x2 of the selection transistor and is connected through a buried electrode 34 to a bit line 35 comprised for example of aluminum. Further, a not shown selection transistor is connected to the other end of the NAND column and has a source diffusion layer connected to a source line formed for example as a diffusion layer in the semiconductor substrate 10.
In the above semiconductor nonvolatile memory device, as shown in FIG. 3A, the element isolation region is formed by an element isolation method using an element isolation trench formed by self-alignment with an end of the floating gate in the channel width direction, that is, the so-called self-aligned shallow trench isolation (SA-STI) method.
As shown in FIG. 3A, the surface of the element isolation insulating film 24a is positioned lower than the floating gate 30b by half of its thickness. Looking at the capacitive coupling between the floating gate 30b and the control gate 31, the electrode area contributing to the capacitive coupling ratio with the floating gate 30b becomes the areas of the side walls and the top surface of the floating gate 30b. 
If designing the above SA-STI cell by the minimum feature size F, a design rule, the area Z of the memory cell of the above SA-STI cell, as shown in FIG. 2A, may b e designed as the theoretically smallest area, that is, Z=4F2.
Therefore, if using the SA-STI cell structure to make a NAND type semiconductor nonvolatile memory device more advantageous for higher integration and thereby increasing the number of memory cells and increasing the area of the memory cell portion, it is possible to make the area of the bit line contact portion, selection MOS transistor portion, and source line portion added negligible compared with the area of the memory cell portion. Therefore, it is possible to fabricate a flash memory with the highest degree of integration within the limit of the minimum feature size.
On the other hand, when forming a floating gate by a quarter micron order of minimum feature size, by making the thickness of the floating gate a quarter micron order as well, the area of the side walls of the floating gate in the channel width direction increases and the electrode area contributing to an increase of the capacitive coupling ratio between the floating gate and control gate can also be increased. Therefore, even without providing a portion of the floating gate projecting out to the element isolation region as in the related art, it is possible to secure a desired value of the capacitive coupling ratio between the floating gate and control gate relating to the voltage of the control gate for giving a desired potential to the floating gate.
Here, an explanation will be given of a method of producing a NAND type flash memory using SA-STI cells of the above configuration, that is, a semiconductor nonvolatile memory device, with reference to FIG. 4A to FIG. 4C and FIGS. 5D to 5E.
First, as shown in FIG. 4A, a tunnel insulating film, that is, the gate insulating film 20, of a floating gate type MOS transistor is formed on the surface of the semiconductor substrate 10 on which is formed a P-type well etc. for isolation of the memory cell portion, peripheral circuit portion, etc. of a NAND type flash memory using for example the thermal oxidation method.
Next, for example, the chemical vapor deposition (CVD) method etc. is used to deposit an impurity-doped polycrystalline silicon and form a floating gate layer 30, then for example, the ordinary pressure CVD method etc. is used to deposit silicon oxide and form a first insulating film 21 at the upper layer of the same.
Next, as shown in FIG. 4B, photolithography is used to pattern the first insulating film 21, floating gate layer 30, and gate insulating film 20 to remove the first insulating film 21, floating gate layer 30, and gate insulating film 20 at the element isolation region. Then, the patterned first insulating film 21a, floating gate layer 30a, and gate insulating film 20a are used as a mask to etch the surface of the semiconductor substrate 10 and form an element isolation trench T. Next, the damage at the time of formation of the element isolation trench T is removed by heat treatment in a nitrogen atmosphere and then thermal oxidation, including protection of the edges of the gate insulating film 20a, is performed to form an element isolation trench covering film 12 comprised of silicon oxide at the inner walls of the element isolation trench T. Note that at the time of thermal oxidation, the side walls of the floating gate layer 30 are also oxidized to form a floating gate covering film 26 of silicon oxide.
Next, the ion implantation method is used to implant for example boron (B) ions and form a channel stopping layer 11 at the bottom of the element isolation trench T.
Next, as shown in FIG. 4C, for example, the reduced pressure CVD method etc. is used to deposit silicon oxide over the entire surface to form the element isolation layer 24 covering the first insulating film 21a and floating gate layer 30a and burying the element isolation trench T.
Next, as shown FIG. 5D, for example, reactive ion etching (RIE) or other etching is used to etch the element isolation layer 24, the first insulating film 21a, and the floating gate covering layer 26 until the position of the surface of the element isolation layer 24 becomes a position below the floating gate layer 30a by about half of its thickness and thereby form an element isolation insulating film 24a. In this etching, part of the sides and the top surface of the floating gate layer 30a are exposed.
Next, as shown in FIG. 5E, an inter-layer insulating film comprised of ONO film is formed covering the exposed surfaces of the floating gate layer 30a. Next, while not illustrated, photolithography is used to remove the inter-layer insulating film other than at the SA-STI cell memory cell portion. Next, a control gate (word line) 31 of a polycide structure comprised of a lower control gate 31a comprised for example of polycrystalline silicon and an upper control gate 31b comprised of tungsten silicide is formed covering the top surface of the inter-layer insulating film. The control gate is used as a mask to etch the floating gate layer 30a and the inter-layer insulating film to form a patterned floating gate 30b and inter-layer insulating film 25a. 
Next, a gate electrode of the selection MOS transistor portion is formed and ions are implanted for formation of the source-drain diffusion regions, methods based on ordinary methods are used to form MOS transistors of the peripheral circuit portion of a NAND type flash memory, for example the CVD method is used to form an inter-layer insulating film 28 of silicon oxide, a contact hole BC reaching the drain diffusion layer 13xe2x80x2 of the selection transistor is formed, a buried electrode 34 and bit line 35 and other interconnections are formed, a passivation film is deposited, a pad opening portion is formed, etc. to form a NAND type flash memory using SA-STI cells as shown in FIG. 3A and FIG. 3B. In FIG. 3A, the illustration of the element isolation trench covering 12 comprised of silicon oxide formed at the inner walls of the element isolation trench T shown in FIG. 5E is omitted.
Turning to the problems to be solved by the invention, the floating gate type semiconductor nonvolatile memory device having the above SA-STI cell structure sometimes suffers from the problems of a lower quality or difficulty in achieving higher integration due to the following problems:
For example, in the above semiconductor nonvolatile memory device, the capacitive coupling of the control gate and floating gate is obtained at the top surface and parts of the side walls of the floating gate. Therefore, if the memory cell area is further reduced, it ends up becoming difficult to secure the necessary capacitive coupling of the control gate and floating gate.
When the necessary capacitive coupling has not been reached, a normal write operation on the memory cell becomes difficult and the quality of the semiconductor nonvolatile memory device ends up falling. To ensure a normal operation, a large operating voltage becomes necessary when generating an FN current in the gate insulating film (tunnel insulating film) to write or erase memory cell data. Since this invites an increase in the area of the booster circuit for boosting the power source voltage to the operating voltage, higher integration of the device becomes difficult. This becomes a factor behind an increase in the chip cost. Further, time is required for boosting, so this also ends up becoming a factor behind a decline in the processing speed.
Further, for example, as shown in FIG. 5E, in the step for forming a control gate (word line) 31 of a polycide structure comprised of a lower control gate 31a comprised of polycrystalline silicon and an upper control gate 31b comprised of tungsten silicide at an upper layer of the inter-layer insulating layer, then using the control gate as a mask to etch the floating gate layer 30a and the inter-layer insulating film to form a patterned floating gate 30b and inter-layer insulating layer 25a, the following problems sometimes arise. In the sectional view along the line C-Cxe2x80x2 in FIG. 2A, in the above step, the control gate 31, inter-layer insulating film 25, and floating gate 30a are removed, but as shown in FIG. 6A, when the control gate 31 and the inter-layer insulating film 25 are removed from the state where the control gate 31 is formed, as shown in FIG. 6B, sometimes as far down as the element isolation insulating film 24a and element isolation trench covering film 12 end up being etched from the top surface. As a result, the surfaces of the element isolation insulating film 24a and the element isolation trench covering film 12 fall and parts of the side walls of the trench type element isolation trench T of the semiconductor substrate 10 are exposed. If the floating gate 30a is removed from this state, then the level as far down as the semiconductor substrate 10 ends up being etched from the exposed parts of the trench type element isolation trench T side walls of the semiconductor substrate 10 as shown in FIG. 6C. A depression V ends up being formed in the semiconductor substrate 10 and the quality of the semiconductor nonvolatile memory device ends up being reduced by a large extent.
An object of the present invention is to provide a semiconductor nonvolatile memory device using SA-STI cells improved in quality and suited for higher integration and a method of producing the same.
According to a first aspect of the present invention, there is provided a semiconductor nonvolatile memory device formed with a plurality of memory transistors, comprising a semiconductor substrate having in its surface a channel formation region in which a channel is formed; a trench formed in the semiconductor substrate so as to divide the channel formation region into a plurality of regions; an element isolation insulating film formed in the trench; a gate insulating film formed on the channel formation region; a first floating gate formed at an upper layer of the gate insulating film; second floating gates formed connected to the first floating gate at facing sides of the first floating gate; an inter-layer insulating film formed at an upper layer of the first floating gate and the second floating gates; a control gate formed at an upper layer of the inter-layer insulating film; and a source-drain region formed connected to the channel formation region.
The semiconductor nonvolatile memory device of the present invention forms a field effect transistor (memory transistor) having a floating gate covered by an insulating film between the control gate and the channel formation region in the semiconductor substrate. If a suitable voltage is applied to the control gate, semiconductor substrate, or source-drain region etc., a Fowler-Nordheim type tunnel current is generated, a charge is injected into the floating gate, or a charge is released from the floating gate to the semiconductor substrate. If a charge is stored in the floating gate in this way, a field is generated due to the stored charge so the threshold voltage of the transistor changes. This changes makes it possible to store data.
The above semiconductor nonvolatile memory device has an element isolation insulating film formed by the SA-STI method and can therefore be reduced in cell area compared with element isolation using a LOCOS element isolation insulating film and is suited to higher integration. Further, since the floating gate has a first floating gate and second floating gates formed connected with the first floating gate at facing sides of the first floating gate, it is possible to increase the surface area contributing to the capacitive coupling ratio with the control gate compared with a floating gate of a conventional shape and to increase the capacitive coupling ratio of the control gate and the floating gate. Due to this, even if the area of the memory cell is reduced, it is possible to secure the necessary capacitive coupling ratio between the control gate and floating gate, prevent erroneous operations at the time of a write operation on a memory cell and a reduction in quality, reduce the operating voltage and the power source voltage, and suppress an increase in the area of the booster circuit and the boosting time.
Therefore, it is possible to provide a semiconductor nonvolatile memory device high in quality and improved In degree of integration.
The semiconductor nonvolatile memory device of the present invention preferably has a plurality of memory transistors connected in a series. A semiconductor nonvolatile memory device comprised of a plurality of NAND type or other memory transistors connected in series is advantageous for increasing the degree of integration. By increasing the number of the memory cells and increasing the area of the memory cell portion, it is possible to make the area of the bit line contact portion, the selection MOS transistor portion, and the source line portion added negligible in extent compared with the area of the memory cell portion and possible to obtain a semiconductor nonvolatile memory device of the highest degree of integration within the limits of the minimum feature size.
Preferably, the semiconductor substrate comprises an insulating film formed on a substrate and a semiconductor layer formed on the insulating film and having the channel formation region and the source-drain region. Due to this, it is possible to make a silicon (semiconductor) on insulator (SOI) structure semiconductor substrate and form a completely element-isolated semiconductor device.
Preferably, when the second floating gates are formed connected to the first floating gate at facing sides of the first floating gate, at least one top point of each of the second floating gates is formed higher than a top portion of the side of the first floating gate connected to it. Due to this, it is possible to obtain a floating gate with at least two facing ends formed higher than the area between the ends, increase the surface area of the floating gate contributing to the capacitive coupling ratio, and increase the capacitive coupling ratio between the control gate and the floating gate.
Preferably, a plurality of the memory transistors are connected in a series. Due to this, it is possible to form a semiconductor nonvolatile memory device of the highest degree of integration within the limit of the minimum feature size. Further, preferably the semiconductor substrate is provided with an insulating film formed on the substrate and, a semiconductor layer formed at an upper layer of the insulating film and having the channel formation region and the source-drain region. Due to this, it is possible to form a completely element-isolated semiconductor device using a semiconductor substrate of an SOI structure.
According to a second aspect of the present invention, there is provided a method of producing a semiconductor nonvolatile memory device comprising the steps of forming a gate insulating film on a semiconductor substrate having a channel formation region; forming a first floating gate at an upper layer of the gate insulating film; forming a mask layer at an upper layer of the first floating gate; forming an element isolation trench in the semiconductor substrate in a region sandwiched between first floating gates; forming an element isolation insulating film by burying an insulator in the element isolation trench; forming a pair of second floating gates connected to a first floating gate at least at facing sides of the first floating gate; removing the mask layer; forming an inter-layer insulating film on the first floating gate and the second floating gates; forming a control gate at an upper layer of the inter-layer insulating film; and forming a source-drain region connected to the channel formation region.
The method of producing the semiconductor nonvolatile memory device of the present invention comprises forming a gate insulating film on a semiconductor substrate having a channel formation region, forming a first floating gate at an upper layer of the gate insulating film, and forming a mask layer at an upper layer of the first floating gate. Next, it forms an element isolation trench in the semiconductor substrate in a region sandwiched between first floating gates and buries the element isolation trench by an insulator to form an element isolation insulating film. Next, it forms a pair of second floating gates connected with the first floating gate at least at facing side walls of the first floating gate. Next, it removes the mask layer, forms an inter-layer insulating film at an upper layer of the first floating gate and the second floating gate, forms a control gate at an upper layer of the inter-layer insulating film, and forms a source-drain region connected to the channel formation region.
According to the method of producing the semiconductor nonvolatile memory device of the present invention, by forming a floating gate comprised of the first floating gate and the pair of second floating gates connected with the first floating gate at the facing side walls of the first floating gate, it becomes possible to increase the surface area contributing to the capacitive coupling ratio with the control gate compared with a floating gate of the shape of the related art and possible to increase the capacitive coupling ratio between the control gate and the floating gate. Due to this, even if the memory cell area is reduced, it is possible to secure the required capacitive coupling ratio of the control gate and floating gate, prevent erroneous operations in a write operation on a memory cells etc. and a fall in quality, reduce the operating voltage and the power source voltage, and suppress an increase in the area of the booster circuit and boosting time.
Further, since a mask layer is formed at an upper layer of the first floating gate, it is possible to form second floating gates by the method of forming a second floating gate layer over the entire surface at an upper layer of the mask layer and removing the second floating gate layer leaving the portions covering the facing side walls of the first floating gate. It is easy to judge the end point when removing the second floating gate layer by making it the time when the mask layer is exposed and fluctuations in the amount of etching can be suppressed for stable production.
Further, in the step of processing the inter-layer insulating film in the pattern of the control gate, the second floating gate becomes a mask for protecting the wall portions of the semiconductor substrate side of the element isolation insulating film to prevent the exposure of parts of the side walls of the element isolation trench formed in the semiconductor substrate, so it becomes possible to prevent etching down to the semiconductor substrate in the step of processing the floating gate in the pattern of the control gate.
Therefore, it becomes possible to produce a semiconductor nonvolatile memory device high in quality and suited for higher integration.
Preferably, the step of forming the element isolation insulating film includes a step of forming an insulator over the entire surface burying the element isolation trench and a step of removing the insulator leaving at least a part thereof buried in the inside of the element isolation trench. Due to this, it is possible to form a trench-type element isolation insulating film by the SA-STI method and possible to reduce the cell area.
Preferably, the step of forming the second floating gates includes a step of forming a second floating gate layer over the entire surface at an upper layer of the mask layer and a step of removing the second floating gate layer leaving at least the parts thereof covering the facing sides of the first floating gate. Due to this, it is possible to easily form a floating gate comprising a first floating gate and a pair of second floating gates connected to the first floating gate at the facing side walls of the first floating gate. Further, since a mask layer is formed at an upper layer of the first floating gate, it is easy to judge the end point when removing the second floating gate layer by making it the time when the mask layer is exposed and fluctuations in the amount of etching can be suppressed for stable production.
Preferably, the step of forming the second floating gates includes a step of forming a second floating gate layer over the entire surface at an upper layer of the mask layer and a step of removing the second floating gate layer leaving the parts thereof covering the facing sides of the mask layer and the first floating gate. Due to this, it becomes possible to make second floating gates higher than the first floating gate by the amount of thickness of the mask layer and increase the surface area contributing to the capacitive coupling ratio.
Preferably, further provision is made, after the step of forming the element isolation trench and before the step of forming the element isolation insulating film, a step of forming a covering film on the surface of the element isolation trench. Due to this, it is possible to remove damage at the time of formation of the element isolation trench and protect the edges of the gate insulating film.